Project
RISC-V Preemptive Multithreaded Kernel
0 entries0 filesC/C++RISC-VISAConcurrency
Projects
Implemented multicore preemptive threading with timer interrupts enabling O(1) forced context switching. Additionally, built synchronization primitives (semaphores, reusable barriers, promises, mutexes).
Implemented multicore preemptive threading with timer interrupts enabling O(1) forced context switching. Additionally, built synchronization primitives (semaphores, reusable barriers, promises, mutexes).
